The present invention relates to the field of buried strap dynamic random access memory (DRAM) devices; more specifically, it relates to a method of reducing buried strap to buried strap punch through in vertical DRAMs.
Integrated circuit devices and especially DRAMs are continually being designed with decreasing dimensions in order to increase performance, decrease the size and increase productivity of integrated circuit chip fabrication. However, certain structures found in some vertical DRAM designs limit the scalability of the DRAM cell.
One type of vertical DRAM comprises a vertical metal oxide semiconductor field effect transistor (MOSFET) formed over a trench capacitor. In vertical DRAMs, the source/drain diffusions of the vertical MOSFET are space apart in a direction perpendicular to the silicon surface (as opposed to a direction parallel to the silicon surface in standard MOSFETS). Often a buried strap acts as both the lowermost source/drain and the connection between the source/drain and the trench capacitor. In this type of vertical DRAM cell, scalability is limited by potential for buried strap to buried strap punch through in adjacent vertical DRAM cells as trench capacitor to trench capacitor spacing is decreased.
Therefore, there is a need for an improved vertical DRAM structure and fabrication method that allow fully scalable vertical DRAM designs.
A first aspect of the present invention is a dynamic random access memory cell comprising: a trench capacitor formed in a silicon substrate; a vertical metal-oxide-silicon field effect transistor formed in a silicon substrate above the trench capacitor, the vertical metal-oxide-silicon field effect transistor having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon subsrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical metal-oxide-silicon field effect transistor, the adjacent vertical metal-oxide-silicon field effect transistor having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and a punch through prevention region disposed between the buried second and third source/drain regions.
A second aspect of the present invention is a method of fabricating a dynamic random access memory cell comprising: providing a trench capacitor formed in a silicon substrate; providing a vertical metal-oxide-silicon field effect transistor formed in the silicon substrate above the trench capacitor, the vertical metal-oxide-silicon field effect transistor having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate elecrode and the channel region; the first source/drain region also belonging to an adjacent vertical metal-oxide-silicon field effect transistor, the adjacent vertical metal-oxide-silicon field effect transistor having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; and forming a punch through prevention region disposed between the buried second and third source/drain regions.
A third aspect of the present invention is a method of fabricating a dynamic random access memory cell comprising: providing a trench capacitor formed in a silicon substrate; providing a vertical metal-oxide-silicon field effect transistor formed in a silicon substrate above the trench capacitor, the vertical metal-oxide-silicon field effect transistor having a gate electrode, a first source/drain region extending from a surface of the silicon substrate into the silicon substrate, a buried second source/drain region electrically contacting the trench capacitor, a channel region formed in the silicon substrate between the first source/drain region and the buried second source/drain region and a gate oxide layer disposed between the gate electrode and the channel region; the first source/drain region also belonging to an adjacent vertical metal-oxide-silicon field effect transistor, the adjacent vertical metal-oxide-silicon field effect transistor having a buried third source/drain region electrically connected to an adjacent trench capacitor, the buried second and third source/drain regions extending toward one another; forming a blocking layer over the surface of the silicon substrate; forming a trench in the blocking layer, the trench aligned between the vertical metal-oxide-silicon field effect transistor and the adjacent the vertical metal-oxide-silicon field effect transistor; and performing an ion implantation to form a punch through prevention region in the silicon substrate aligned under the trench and disposed between the buried second and third source/drain regions, the blocking layer blocking the ion implantation from reaching the silicon substrate.